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<p>This typedef contains IP hardware configuration information.  
 <a href="struct_x_dma_pcie___config.html#details">More...</a></p>
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Data Fields</h2></td></tr>
<tr class="memitem:a05db311d17be7c1b6e270fa80fba9e16"><td class="memItemLeft" align="right" valign="top">u16&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dma_pcie___config.html#a05db311d17be7c1b6e270fa80fba9e16">DeviceId</a></td></tr>
<tr class="memdesc:a05db311d17be7c1b6e270fa80fba9e16"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unique ID of PCIe IP.  <a href="#a05db311d17be7c1b6e270fa80fba9e16">More...</a><br/></td></tr>
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<tr class="memitem:a11981cd817dda09fa8ffb1e4b6c524bd"><td class="memItemLeft" align="right" valign="top">UINTPTR&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dma_pcie___config.html#a11981cd817dda09fa8ffb1e4b6c524bd">BaseAddress</a></td></tr>
<tr class="memdesc:a11981cd817dda09fa8ffb1e4b6c524bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register base address.  <a href="#a11981cd817dda09fa8ffb1e4b6c524bd">More...</a><br/></td></tr>
<tr class="separator:a11981cd817dda09fa8ffb1e4b6c524bd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab67ad06680c60071c889da0a04852a96"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dma_pcie___config.html#ab67ad06680c60071c889da0a04852a96">IncludeRootComplex</a></td></tr>
<tr class="memdesc:ab67ad06680c60071c889da0a04852a96"><td class="mdescLeft">&#160;</td><td class="mdescRight">Is IP built as root complex.  <a href="#ab67ad06680c60071c889da0a04852a96">More...</a><br/></td></tr>
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<tr class="memitem:a7817941b09b07386d149f37f1a98c4bd"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dma_pcie___config.html#a7817941b09b07386d149f37f1a98c4bd">Ecam</a></td></tr>
<tr class="memdesc:a7817941b09b07386d149f37f1a98c4bd"><td class="mdescLeft">&#160;</td><td class="mdescRight">IATU Region Address for versal2.  <a href="#a7817941b09b07386d149f37f1a98c4bd">More...</a><br/></td></tr>
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<tr class="memitem:a154ea2174bdb4f7e8b9ef9e11f857c4e"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dma_pcie___config.html#a154ea2174bdb4f7e8b9ef9e11f857c4e">NpMemBaseAddr</a></td></tr>
<tr class="memdesc:a154ea2174bdb4f7e8b9ef9e11f857c4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">non prefetchable memory base address  <a href="#a154ea2174bdb4f7e8b9ef9e11f857c4e">More...</a><br/></td></tr>
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<tr class="memitem:aaaff93f64f134d510ad5c5e5a326be9b"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_x_dma_pcie___config.html#aaaff93f64f134d510ad5c5e5a326be9b">NpMemMaxAddr</a></td></tr>
<tr class="memdesc:aaaff93f64f134d510ad5c5e5a326be9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">non prefetchable memory max base address  <a href="#aaaff93f64f134d510ad5c5e5a326be9b">More...</a><br/></td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>This typedef contains IP hardware configuration information. </p>
</div><h2 class="groupheader">Field Documentation</h2>
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<p>Register base address. </p>

<p>Referenced by <a class="el" href="xdmapcie__rc__enumerate__example_8c.html#aa1e7ab3bea37defba5bf6590492c9b3c">PcieInitRootComplex()</a>, <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>, <a class="el" href="xdmapcie__intr_8c.html#a1ba2488b5b13dfebf7a3df93c300d67e">XDmaPcie_ClearPendingInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a8ae44f206a94bf40daea49281112b46d">XDmaPcie_ClearRootPortErrFIFOMsg()</a>, <a class="el" href="xdmapcie_8h.html#a1a9e71d1904e3b6bfca811f5baec640c">XDmaPcie_ClearRootPortIntFIFOReg()</a>, <a class="el" href="xdmapcie__intr_8c.html#a3130feda681a6630a2c1d0cb77a2d868">XDmaPcie_DisableGlobalInterrupt()</a>, <a class="el" href="xdmapcie__intr_8c.html#a086244f1e8866721dbb016893814281a">XDmaPcie_DisableInterrupts()</a>, <a class="el" href="xdmapcie__intr_8c.html#a60093f2ef3dd433de9da51dadc1e46bc">XDmaPcie_EnableGlobalInterrupt()</a>, <a class="el" href="xdmapcie__intr_8c.html#a034dab86e9626ac44e222373d056f693">XDmaPcie_EnableInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a83357e666376be50d018b3e0d2d07acf">XDmaPcie_GetBridgeInfo()</a>, <a class="el" href="xdmapcie__intr_8c.html#a7f0db923538acc2ee66a3011f1abf32c">XDmaPcie_GetEnabledInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a2c9b0cae150260c8ee67c21c3e7cd372">XDmaPcie_GetLocalBusBar2PcieBar()</a>, <a class="el" href="xdmapcie__intr_8c.html#afbcdc92c0afe5f15363ceea6dd2472be">XDmaPcie_GetPendingInterrupts()</a>, <a class="el" href="xdmapcie_8h.html#a3533208a920e43d2e9442ca9b02a22a3">XDmaPcie_GetPhyStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#a5f24eea699cbc956a9705034c5f12607">XDmaPcie_GetRequesterId()</a>, <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>, <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>, <a class="el" href="xdmapcie_8h.html#a2baa98cfc13d1f4d209267e80808e3b8">XDmaPcie_GetRootPortStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#ac61d1050938321b594087912a2272efb">XDmaPcie_GetVsecCapability()</a>, <a class="el" href="xdmapcie_8h.html#acf9acbd19090d9147cdad13913354fa6">XDmaPcie_GetVsecHeader()</a>, <a class="el" href="xdmapcie_8h.html#a0b168437da7bb05a2cdcbc2267df272d">XDmaPcie_ReadLocalConfigSpace()</a>, <a class="el" href="xdmapcie_8h.html#af399300a4c8de88e4545ec848acfbca3">XDmaPcie_SetLocalBusBar2PcieBar()</a>, <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>, <a class="el" href="xdmapcie_8h.html#a1f829c82bb17dcc56648246fafa2eaa5">XDmaPcie_SetRootPortStatusCtrl()</a>, and <a class="el" href="xdmapcie_8h.html#aeedb6585a8dcbcc40443e7b90932ad6c">XDmaPcie_WriteLocalConfigSpace()</a>.</p>

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<p>Unique ID of PCIe IP. </p>

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<p>IATU Region Address for versal2. </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>, <a class="el" href="xdmapcie__caps_8c.html#ac232d6bc0efdff01bf3aff950049cf27">XDmaPcie_GetCapability()</a>, <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>, and <a class="el" href="xdmapcie_8h.html#ad47beee6caa44ae3f91979be9cd531bf">XDmaPcie_WriteRemoteConfigSpace()</a>.</p>

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<p>Is IP built as root complex. </p>

<p>Referenced by <a class="el" href="xdmapcie__rc__enumerate__example_8c.html#aa1e7ab3bea37defba5bf6590492c9b3c">PcieInitRootComplex()</a>, <a class="el" href="xdmapcie_8h.html#a8ae44f206a94bf40daea49281112b46d">XDmaPcie_ClearRootPortErrFIFOMsg()</a>, <a class="el" href="xdmapcie_8h.html#a1a9e71d1904e3b6bfca811f5baec640c">XDmaPcie_ClearRootPortIntFIFOReg()</a>, <a class="el" href="xdmapcie_8h.html#afc77bc991235ea37d13d7bd07032584e">XDmaPcie_GetRootPortErrFIFOMsg()</a>, <a class="el" href="xdmapcie_8h.html#a54d41c333a761b1c8decb59c19f1ffc6">XDmaPcie_GetRootPortIntFIFOReg()</a>, <a class="el" href="xdmapcie_8h.html#a2baa98cfc13d1f4d209267e80808e3b8">XDmaPcie_GetRootPortStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#adac6261cddb63084c8ee87518e99edef">XDmaPcie_ReadRemoteConfigSpace()</a>, <a class="el" href="xdmapcie_8h.html#a1641602833f00b16132be700a66e2f93">XDmaPcie_SetRootPortMSIBase()</a>, <a class="el" href="xdmapcie_8h.html#a1f829c82bb17dcc56648246fafa2eaa5">XDmaPcie_SetRootPortStatusCtrl()</a>, <a class="el" href="xdmapcie_8h.html#aeedb6585a8dcbcc40443e7b90932ad6c">XDmaPcie_WriteLocalConfigSpace()</a>, and <a class="el" href="xdmapcie_8h.html#ad47beee6caa44ae3f91979be9cd531bf">XDmaPcie_WriteRemoteConfigSpace()</a>.</p>

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<p>non prefetchable memory base address </p>

<p>Referenced by <a class="el" href="xdmapcie_8h.html#a557a92506060fd460154426bd8c4870c">XDmaPcie_CfgInitialize()</a>.</p>

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<p>non prefetchable memory max base address </p>

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